Hierarchical matrices approximate specific types of dense matrices, e.g., from discretized integral equations, kernel-based approximation and Gaussian process regression, leading to log-linear time complexity in dense matrix-vector products. To be able to solve large-scale applications, H-matrix algorithms have to be parallelized. A special kind of parallel hardware are many-core processors, e.g. graphics processing units (GPUs). The parallelization of H-matrices on many-core processors is difficult due to the complex nature of the underlying algorithms that need to be mapped to rather simple parallel operations.

We are interested to use these many-core processors for the full H-matrix construction and application process. A motivation for this interest lies in the well-known claim that future standard processors will evolve towards many-core hardware, anyway. In order to be prepared for this development, we want to discuss many-core parallel formulations of classical H-matrix algorithms and adaptive cross approximations.

In the presentation, the use of H-matrices is motivated by the model application of kernel-based approximation for the solution of parametric PDEs, e.g. PDEs with stochastic coefficients. The main part of the talk will be dedicated to the challenges of H-matrix parallelizations on many-core hardware with the specific model hardware of GPUs. We propose a set of parallelization strategies which overcome most of these challenges. Benchmarks of our implementation are used to explain the effect of different parallel formulations of the algorithms.